1. Field of the Invention
The present invention relates to a process for manufacturing isolated semi conductor components in a semi conductor wafer and, more particularly to a process compatible with semi conductor substrates of the type used in bipolar technology; that is to say a technology in which an epitaxied layer of a second type of conductivity is formed on a substrate of the first type of conductivity, buried layers of the second type of conductivity being possibly provided at localized chosen positions at the interface between the substrate and the epitaxied layer.
2. Description of the Prior Art
Usually, in bipolar technology, the different individual components of an integrated circuit are placed in zones surrounded by insulating walls, but the bottom of these zones corresponds to the substrate or to a buried layer and does not actually rest on an insulating layer, the insulation being obtained by a PN junction provided that the substrate is suitably biased. This lack of real insulation of the bottom of the caissons may, in some cases, adversely affect the correct operation of the integrated circuit and in any case complicate the task of the designer who must always plan for the substrate to be at an extreme biasing level. In addition, different parasitic effects occur because the substrate may form one of the layers of a parasitic transistor or thyristor.
It is desirable in practice to be able to make use of a bipolar integrated circuit having at least a number of MOS or bipolar transistors completely insulated from the substrate or in which at least the drain, source, collector or emitter layers are insulated from this substrate. The object of the present invention is to provide such components and a process for manufacturing these components compatible with bipolar integrated circuit technology.